• Half (16-bit) Precision
• Near IEEE-754R compliance in hardware
• Full IEEE-754R compliance with software support
• Flush-to-Zero underflow implementation
• Optional divide unit
• 1-stage pipeline for max performance in low power systems
• Generic function unit interface
• Fully synthesize-able
• Low gate count, ~10K (w/o divide), ~14K (w/ divide) NAND2 gates

FPHZ Datasheet