• Single (32-bit) Precision
• User configurable register file (4-16 registers)
• ARM7® co-processor interface
• Near IEEE-754 compliance in hardware
• Full IEEE-754 compliance with software support
• Flush-to-Zero underflow implementation
• 1-stage pipeline for max performance in low power systems
• Fully synthesize-able
• Low gate count, ~40K NAND2 gates

A7FPSZ Datasheet